1. Field of the Invention
The invention relates to a method for fabricating a thin film transistor and related circuits, and more particularly, to a method with improved carrier mobility and stable threshold voltage.
2. Description of the Prior Art
In recent years, various display techniques have been developed flourishingly. After continuous research and development, new products such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diode (OLED) displays have been gradually commercialized and applied to various display apparatuses with different sizes. Without any exception, all of the manufacturers today are developing toward high brightness and high efficiency for fabricating a much more commercially profitable display. Among numerous flat display techniques developed today, liquid crystal displays have been considered as one of the most mature techniques. Evidently, electronic products including cellular phones, digital cameras, camcorders, notebook computers, and numerous other monitoring devices commonly used today are all variations of this technique.
In general, the transparency and the coloring of liquid crystal displays are controlled by the spinning of liquid crystal molecules, and by adjusting the transparency, the brightness of the display can also controlled. Essentially, when the color of the display remains unchanged, the position of the liquid crystal molecules also remains unchanged. Hence, the liquid crystal displays are characterized by advantages such as non-flashy and stable graphics. Despite the fact that the OLED has been developed later than the liquid crystal display (LCD), it still contains numerous beneficial characteristics, including a spontaneous light source, a wide viewing angle, quick response, low power consumption, high contrast and brightness, small thickness, full-color capability, simple structure, and a wide range of operating temperatures. All in all, the OLED has been applied extensively in various industries.
In addition, liquid crystal displays and organic light emitting diode displays are also active matrix displays driven by thin film transistors. The term active driving literally means the fabrication of numerous electronic devices including thin film transistors lined up in the form of arrays, pixel electrodes, interlinking scan lines and signal lines on the liquid crystal display, and several other devices in combination with corresponding capacitors and connection pad. The driving of a liquid crystal display essentially involves the driving of each pixel electrode by its independently driven circuit. In other words, when the thin film transistor within each independently driven circuit is turned on, a predetermined voltage will be sent to the corresponding pixel electrode and initiates the display to generate a picture. In contrast to a passive matrix display that adopts the method of driving the scan lines of the display in sequence thereby driving pixels in different rows sequentially, the light-emitting time of each pixel of the active matrix display is not restricted by the scanning frequency and the number of scan lines. Hence, the fabrication of the thin film transistor and its corresponding circuit is a critical stage in producing a large-size and high-resolution liquid crystal display.
Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 are schematic diagrams showing a method for fabricating at least one thin film transistor according to the prior art. As shown in FIG. 1, the thin film transistor of the prior art is a bottom gate structure. The thin film transistor 26 is essentially fabricated on an insulation substrate 10. The substrate 10 is comprised of a transparent material, such as a glass substrate, a quartz substrate, or a plastic substrate. The surface of the insulation substrate 10 further includes a predetermined source region 11, a predetermined drain region 12, and a predetermined channel region 13. A first sputtering process is performed first to form a first metal layer (not shown) on a surface of the insulation substrate 10. The first metal layer (not shown) is a tungsten layer, a tantalum layer, or other conductive metal layer. Next, a first photo-etching-process (PEP) is performed to form a gate electrode 14 on the surface of the insulation substrate 10. The gate electrode 14 is also positioned on top of the predetermined channel region 13.
Next, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer 16 as a gate insulation layer on the surface of the gate electrode 14 and the insulation substrate 10. Next, a semiconductor layer 18 is formed on top of the silicon nitride layer 16. Also referred to as the active layer, the semiconductor layer 18 is a hydrogen-contained amorphous silicon layer that is also used as a passageway when the thin film transistor (not shown) is turned on. Next, an n+ doped Si layer 22 comprising amorphous silicon doped with phosphor is deposited on top of the semiconductor layer 18.
As shown in FIG. 2, a second photo-etching-process is performed to remove part of the semiconductor layer 18 and the n+ doped Si layer 22. By utilizing a second sputtering process, a second metal layer 24 is formed on top of the n+ doped Si layer 22, semiconductor layer 18, and the silicon nitride layer 14. The second metal layer 24 is comprised of molybdenum, chrome, or tungsten.
As shown in FIG. 3, a third photo-etching-process is performed to form a source electrode 28 and a drain electrode 32 of a thin film transistor 26 between the second metal layer 24 and to expose a semiconductor layer 18 on top of the predetermined channel region 13. The source electrode 28 is located on top of the predetermined source region 11, part of the silicon nitride layer 16, and the doped n+ layer 22 whereas the drain electrode 32 is located on top of the predetermined drain region 12, part of the silicon nitride layer 16, and the n+ doped Si layer 22. The n+ doped Si layer 22 functions to increase the Ohmic contact ability of the second metal layer 24 to the semiconductor layer 18 and ultimately reduces various problems caused by direct contact between the second metal layer 24 and the semiconductor layer 18 as a result of a significant difference in work function.
After the deposition of a dielectric layer 34, a fourth photo-etching-process is performed within the dielectric layer 34 that is located on top of the predetermined source region 111 and the predetermined drain region 12 to form a contact hole 36 that extends directly to the source electrode 28 and the drain electrode 32. After the contact hole 36 is filled with conducting materials, the source electrode 28 and the drain electrode 32 are electrically connected to a capacitor plate or an image signal line (both not shown) via a contact plug 38 to complete an electrical circuit.
Nevertheless, the fabrication method of the thin film transistor 26 according to the prior art often produces a serious problem. Since the semiconductor layer 18 is comprised of a hydrogen-contained amorphous silicon material, the mobility of the carriers often becomes limited when the thin film transistor 26 is turned on, thereby influencing the overall driving speed. Conversely, the electrical leakage also becomes excessively large when the thin film transistor 26 is turned off. At the same time, as the amorphous silicon is not defined by a specific structure, a meta-stable dangling bond phenomenon often results when any silicon atom is lacking one of its bonding atoms. The dangling bond phenomenon is essentially a defect that ultimately grabs electrons or disrupts the flow of the electrons. However, as the semiconductor layer 18 is a hydrogen-contained amorphous silicon layer, the hydrogen atom will readily combine with the silicon atom to form a bond at the location where the dangling bond is produced. Also, due to the fact that the hydrogen atom diffuses easily into the interface (a Si/SiNx interface) of the semiconductor layer 18 and the silicon nitride layer 16 and the discontinuous nature of the Si/SiNx interface, the hydrogen atom is easily trapped inside the Si/SiNx interface and eventually becomes an interface-trapped charge. In essence, the threshold voltage of a thin film transistor is the smallest gate voltage required when a strong inversion is generated at the semiconductor surface. The threshold voltage and the flat-band voltage are closely related and by generating the interface-trapped charge, the size of the flat-band voltage is altered and the stability and the life expectancy of the thin film transistor 26 are also greatly influenced.
As a result, another method has been developed according to the prior art for transforming the amorphous silicon material to a polysilicon material. Please refer to FIG. 4. FIG. 4 is a schematic diagram showing the means by which an amorphous silicon layer is processed via an excimer laser annealing process according to the prior art. As shown in FIG. 4, an excimer laser annealing process is performed after the formation of the amorphous silicon thin film 52 is formed and the insulation substrate 50 is placed into a closed chamber (not shown). When the excimer laser annealing process is performed, the amorphous silicon thin film 52 of the insulation substrate 50 is irradiated directly by an excimer laser pulse 54 through a transparent window (not shown) on top of the closed chamber. In addition, a predetermined area is also scanned by the laser pulse to rapidly heat up the amorphous silicon thin film 52 contained within the predetermined area. By absorbing the ultraviolet light from the laser, the amorphous silicon thin film 52 is rapidly melted and recrystallized to form polysilicon material.
However, the method stated previously also causes other serious problems. First, an extra excimer laser annealing step is added to the fabrication process and thereby significantly increases the overall time and cost. Secondly, when an excimer laser annealing process is performed, numerous variables are required to be controlled simultaneously. The variables include the hydrogen content of the amorphous silicon thin film, the thickness and smoothness of the thin film surface, the energy density of the laser, the spatial distribution of the laser, the degree of overlapping of the laser pulse, and the temperature and surrounding environmental atmosphere when the laser annealing process is performed. Typically, the quality of the active polysilicon thin film within the passageway becomes difficult to control if the fabrication process is not properly regulated. In addition, the laser crystallization process is essentially a low temperature solid phase recrystallization process that characterizes a long processing time. Consequently, the grains are only able to grow to a certain size and the grain size is also difficult to control. Eventually, the overall carrier mobility and the control of electrical leakage are greatly affected.
Therefore, it becomes a great challenge to develop a fabrication process that is capable of producing a semiconductor layer containing an expected microcrystalline structure and achieving a satisfactory carrier mobility and low electrical leakage by utilizing the semiconductor layer as an active layer of a thin film transistor.